1. Field of the Invention
The invention relates generally to the metrological characterization and processing of substrates such as semiconductor wafers. In particular, the invention relates to methods and associated technologies that account and/or compensate for misalignment and overlay error issues associated with lithographic processing of semiconductor wafers.
2. Description of Background Art
Fabricating micro-electronic circuit and other microstructural features on a substrate typically involves the use of photolithographic technology. Such technology may include wafer processing that requires several photolithographic steps or stages to create the entire structure or circuit in layers or levels. Photolithography tools are often incorporated in production lines for carrying out a wafer process in successive stages. Each stage may be set up to carry out a subprocess of the wafer process. At least one subprocess may be a photolithographic process that requires use of a photolithography tool.
The effectiveness of photolithographic processes depends, often in part, on the alignment of a substrate under processing (or surface and/or interior features thereof) with respect to a mask used in the optical exposure of the photolithographic process. Misalignment of a substrate under processing with respect to the mask is undesirable and can occur due to various causes. For example, when misalignment exceeds the tolerance range, a resultant circuit may be rendered defective, thereby causing poor performance or even failure of the circuit.
In some instances, misalignment due to wafer warpage may lead to photolithography focus problems. Such focus problems are described in U.S. patent application Ser. No. 11/638,650, entitled “WAFER SCREENING AND WAFER PROCESSING CONTROL BASED ON MONITORING OF DEPTH OF FOCUS,” filed Dec. 13, 2006, by inventor David Owen, assigned to Ultratech, Inc. This patent application also describes methods and production lines for carrying out a photolithographic process in which interferometry may be used to determine whether one or more locations on a wafer surface would or would likely to be out of focus in a photolithography tool associated with the photolithographic process.
In various lithographic systems, one or more alignment mechanisms are provided to align features with sufficient precision to overlay features in a given layer with respect to features in a prior level. In some implementations, direct measurements of the position of alignment marks or features may be used as part of the configuration or setup of a specific lithography process to optimize alignment or overlay of different layers with respect to one another. Such systems can be configured to compensate or modify the printing of features when the evaluation of alignment mark positions indicate that the actual position of the marks deviates from the nominal position. The required overlay precision scales with the size of the features being printed in some applications and the overlay precision may be on the order of 10 to 20 nanometers in some systems.
In addition, certain stages of production lines for wafer processing are more costly to setup, maintain and/or operate than others. For example, a particularly costly stage of a production line may employ a photolithography tool that requires a strict processing alignment tolerance and/or wafer quality. Loading of wafers of unacceptable quality or in an unacceptable manner into such a tool wastes tool operation time, increases the cost of the wafer process, and reduces the overall efficiency of the wafer process.
There are a number of ways in which quality control measures may be introduced in production lines that engage in wafer processing. For example, image-processing techniques may be used as a direct measurement of misalignment and overlay error. In general, such techniques are impractical because they are too time consuming. In addition, such techniques tend to emphasize magnitude over directionality and generally require the use of alignment marks or targets. By definition, alignment marks or targets are in the proximity of, but not at the exact location of devices. Accordingly, such techniques, while potentially suitable for localized measurements, lack wafer-scale or “global” accuracy. In short, known techniques are generally more microscale in nature and are not necessarily suitable for macroscale wafer evaluations.
Thus, there is a need to address such alignment issues in the context of photolithography. In particular, there is a need for technologies that allow for early, fast, accurate, robust, information-rich, and wholistic sorting of “good” wafers from “bad” in production lines that carry out wafer processes so as to improve line resource utilization.